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MAX1473
315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
Pin Description
PIN
TSSOP TQFN
NAME
FUNCTION
1
29
XTAL1
1st Crystal Input. (See the Phase-Locked Loop section.)
Positive Analog Supply Voltage. For +5V operation, pin 2 is the output of an on-chip +3.2V
low-dropout regulator and should be bypassed to AGND with a 0.1μF capacitor as close as
2, 7
4, 30
AVDD
possible to the pin. Pin 7 must be externally connected to the supply from pin 2 and bypassed to
AGND with a 0.01μF capacitor as close as possible to the pin (see the Voltage Regulator section
and the Typical Application Circuit ).
3
4
5
6
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
31
32
2
3
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
22
LNAIN
LNASRC
AGND
LNAOUT
MIXIN1
MIXIN2
AGND
IRSEL
MIXOUT
DGND
DVDD
AGCDIS
XTALSEL
IFIN1
IFIN2
DFO
DSN
OPP
DFFB
DSP
Low-Noise Amplifier Input. (See the Low-Noise Amplifier section.)
Low-Noise Amplifier Source for External Inductive Degeneration. Connect inductor to ground to set
LNA input impedance. (See the Low-Noise Amplifier section.)
Analog Ground
Low-Noise Amplifier Output. Connect to mixer through an LC tank filter. (See the Low-Noise
Amplifier section.)
1st Differential Mixer Input. Connect through a 100pF capacitor to V DD3 side of the LC tank.
2nd Differential Mixer Input. Connect through a 100pF capacitor to LC tank filter from LNAOUT.
Analog Ground
Image Rejection Select Pin. Set V IRSEL = 0V to center image rejection at 315MHz. Leave IRSEL
unconnected to center image rejection at 375MHz. Set V IRSEL = V DD to center image rejection at 433MHz.
330 ? Mixer Output. Connect to the input of the 10.7MHz bandpass filter.
Digital Ground
Positive Digital Supply Voltage. Connect to both of the AVDD pins. Bypass to DGND with a 0.01μF
capacitor as close as possible to the pin (see the Typical Application Circuit ).
AGC Control Pin. Pull high to disable AGC.
Crystal Divider Ratio Select Pin. Drive XTALSEL low to select divider ratio of 64, or drive XTALSEL
high to select divider ratio of 32.
1st Differential Intermediate Frequency Limiter Amplifier Input. Decouple to AGND with a 1500pF
capacitor.
2nd Differential Intermediate Frequency Limiter Amplifier Input. Connect to the output of a 10.7MHz
bandpass filter.
Data Filter Output
Negative Data Slicer Input
Noninverting Op-Amp Input for the Sallen-Key Data Filter
Data Filter Feedback Node. Input for the feedback of the Sallen-Key data filter.
Positive Data Slicer Input
+5V Supply Voltage. Bypass to AGND with a 0.01μF capacitor as close as possible to the pin. For
24
23
V DD5
+5V operation, V DD5 is the input to an on-chip voltage regulator whose +3.2V output appears at the
pin 2 AVDD pin. (See the Voltage Regulator section and the Typical Application Circuit .)
25
24
DATAOUT Digital Baseband Data Output
8
26
27
28
—
—
26
27
28
1, 13,
21, 25
—
PDOUT
PWRDN
XTAL2
N.C.
EP
Peak Detector Output
Power-Down Select Input. Drive this pin with a logic high to power on the IC.
2nd Crystal Input
No Connection
Exposed Pad (TQFN Only). Connect EP to GND.
Maxim Integrated
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